Pravar Pathania

I am an undergraduate researcher at IIIT-Delhi pursuing a B.Tech. in Electronics and VLSI. My work spans computer architecture, memory systems, hardware-software co-design, and edge inference accelerators. I am broadly interested in building efficient microarchitectural systems at the intersection of hardware and software.

  

News

Jan 2026Started as Research Intern at IIT Bombay, working with Prof. Biswabandan Panda.
Jan 2026Joined the Artifact Evaluation Committee for IEEE/ACM HPCA 2026.
Nov 2025Won 2nd Place (Undergraduate) at the ACM Student Research Competition, IEEE/ACM MICRO 2025.
Sep 2025Paper accepted at IEEE International System-on-Chip Conference (SoCC) 2025.
Jun 2025Started as Research Intern at the University of Sydney, working with Prof. Sri Parameswaran.

Research Interests

  • Computer Architecture: memory systems and microarchitectural policy design
  • Hardware-Software Co-Design: RISC-V systems, SoC integration, FPGA prototyping
  • Edge Computing: CNN accelerators and energy-efficient inference
  • Intermittent Computing: checkpoint optimization for energy-harvesting systems

Publications

EASE: An Energy-Aware Skip and Execute Mechanism for Efficient Intermittent Computing
Under submission — ICCAD 2026
Pravar Pathania, Namit Gupta, Keshav Goel, Anuj Grover, Sujay Deb

CoDe-CS: A CNN Accelerator with Co-Designed Compute and Storage for Edge Efficiency
IEEE International System-on-Chip Conference (SoCC) 2025
Pravar Pathania, Namit Gupta, Vishal Kumar, Keshav Goel, Sujay Deb

Open Source SoC Design for Low-Cost Micro Weather Station
IEEE International Symposium on Smart Electronic Systems (iSES) 2024
Namit Gupta, Pravar Pathania, Keshav Goel, Tarun Sharma, Sujay Deb

Research Experience

Research Intern, IIT Bombay  ·  Jan 2026 – Present
Guide: Prof. Biswabandan Panda
Investigating cache management policies for modern DRAM architectures.

Research Intern, University of Sydney  ·  Jun 2025 – Sep 2025
Guide: Prof. Sri Parameswaran
Extended the Gemmini accelerator with custom RISC-V ISA extensions for mixed-precision DNN execution in Chipyard.

Research Assistant, IIIT-Delhi  ·  Jun 2025 – Present
Guide: Prof. Sujay Deb, Prof. Anuj Grover
Designing adaptive checkpointing mechanisms for intermittent computing systems.

Research Assistant, IIIT-Delhi  ·  May 2024 – May 2025
Guide: Prof. Sujay Deb
Designed a co-optimised CNN accelerator with parameterised PE arrays and column-stationary dataflow for edge inference. Published at IEEE SoCC 2025.

Research Assistant, IIIT-Delhi  ·  Dec 2023 – May 2024
Guide: Prof. Sujay Deb
Designed and validated a SystemVerilog SoC around the Ibex core with memory-mapped peripherals on FPGA.

Education

Indraprastha Institute of Information Technology, Delhi
B.Tech. in Electronics and VLSI  ·  Nov 2022 – May 2026

Awards & Honors

  • 2nd Place (Undergraduate), ACM Student Research Competition — IEEE/ACM MICRO 2025

Academic Service

  • Artifact Evaluator, IEEE/ACM HPCA 2026

Technical Skills

  • RTL Design: Verilog, SystemVerilog, Chisel
  • Architecture & Simulation: ChampSim, gem5, Chipyard, Spike
  • Programming: C/C++, Python
  • Tools: Vivado, Vitis HLS, Verilator, Cadence Virtuoso